Rambus has announced an enhancement to its data centre security offering with the introduction of CryptoManager Root of Trust that supports the Caliptra specification.
The solution provides a production-ready security and orchestration subsystem intended for use in enterprise and AI system-on-chips (SoCs) that power major data centre operations.
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The CryptoManager Root of Trust is interoperable with the open Caliptra framework, a platform dedicated to device security within data centre-class silicon.
Caliptra is an open-source Root of Trust developed for integration into central processing units (CPUs), graphics processing units (GPUs), AI accelerators, networking devices and related infrastructure.
Created initially through the Open Compute Project and now overseen by the CHIPS Alliance, Caliptra combines hardware, firmware, and specifications to allow for unified identity, measured boot, and attestation across varied devices.
With this latest update, Rambus says semiconductor designers are able to leverage the open-source Caliptra foundation and deploy a full security subsystem into their products.
This integration is intended to streamline platform-wide security, provide orchestration for security workflows, defend against a range of attack vectors, and meet evolving cryptographic requirements.
The supporting software and commercial support aim to maintain device security throughout its operational lifecycle.
Rambus Silicon IP senior vice-president and general manager Simon Blake-Wilson said: “As the Caliptra ecosystem gains momentum, organisations need a practical path to deploy scalable and supportable security solutions in demanding production environments.
“CryptoManager Root of Trust supporting the Caliptra specification provides the hardware, software, advanced protections and commercial support needed to accelerate deployment of differentiated, enterprise-grade security that is interoperable with the Caliptra framework.”
The solution includes a secure reduced instruction set computer V (RISC-V) processor, protected memory, secure data storage, cryptographic accelerators and secure interfaces.
Designed to operate alongside an unmodified Caliptra core, it manages interactions within the SoC while confining sensitive operations to a dedicated security boundary.
The technology supports a range of cryptographic standards including classical, post-quantum, and regional algorithms, and is positioned for FIPS 140-3 and SESIP certifications.
